1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication and design, and more particularly, to modifying a layout of an IC based on a function of an interconnect, and a related circuit and design structure.
2. Background Art
In the integrated circuit (IC) chip industry, layouts of an IC and related groundrules are typically arranged to accommodate minimum metal line density, high speed performance, minimize capacitance such that voltages can scale downwardly (e.g., <5 V). New technology, however, may use structures that have functions that are not accommodated by current groundrules. For example, high voltage applications (e.g., >30 V) present a number of issues such as shorting issues not envisioned by current groundrules. Where copper (Cu) wiring is used this situation becomes more complicated. For example, fill shapes used with copper wiring need to be modified to accommodate the high voltage applications. In particular, breakdown fields in back end of line (BEOL) materials may be between 3 and 5 MV/cm depending on the material used (e.g., low dielectric constant material (low-k) or oxides). This breakdown range requires larger spacing between interconnects and/or fill shapes to accommodate the higher voltages. Thus, the breakdown range may require new groundrules and/or new restrictions on fill shapes and interconnect spacing. Other structures having specialized functions may also not be accommodated by current groundrules.